The MAX3882A is a deserializer combined with clock and data recovery and limiting amplifier ideal for converting 2.488Gbps serial data to 4-bit-wide, 622Mbps parallel data for SDH/SONET applications. The device accepts serial NRZ input data as low as 10mVP-P of 2.488Gbps and generates four parallel LVDS data outputs at 622Mbps. Included is an additional high-speed serial data input for system loopback diagnostic testing. For data acquisition, the MAX3882A does not require an external reference clock. However, if needed, the loopback input can be connected to an external reference clock of 155MHz or 622MHz to maintain a valid clock output in the absence of input data transitions. Additionally, a TTL-compatible loss-of-lock output is provided. The device provides a vertical threshold adjustment to compensate for optical noise generated by EDFAs in WDM transmission systems. The MAX3882A operates from a single +3.3V supply and consumes 610mW.
The MAX3882A's jitter performance exceeds all SDH/SONET specifications. The device is available in a 6mm x 6mm, 36-pin TQFN package.
주요기능
애플리케이션/용도
No Reference Clock Required for Data Acquisition
Serial Input Rate: 2.488Gbps
Fully Integrated Clock and Data Recovery with Limiting Amplifier and 1:4 Demultiplexer
Parallel Output Rate: 622Mbps
Differential Input Range: 10mVP-P to 1.6VP-P without Threshold Adjust
Differential Input Range: 50mVP-P to 600mVP-P with Threshold Adjust
0.65UI High-Frequency Jitter Tolerance
Loss-of-Lock (Active-Low LOL) Indicator
Wide Input Threshold Adjust Range: ±170mV
Maintain Valid Clock Output in Absence of Data Transitions
System Loopback Input Available for System Diagnostic Testing
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부품번호 suffix: T 또는 T&R = 테잎 앤 릴,
+ = RoHS/lead-free,
# = RoHS/lead 예외.추가 정보: 전체 데이터 시트 또는 부품번호 규칙
*일부 패키지는 크기 편차(variation)를 가지며 이 값은 도면 상에 제시되어 있습니다. “패키지 코드/편차”는 해당 제품이 사용하고 있는 편차를 보여줍니다. 부품번호 suffix에 "+", "#", "-"는 RoHS 준수 상태를 나타냅니다. 패키지 도면에 suffix 문자는 다를 수 있습니다.
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