The MAX3877/MAX3878 are compact, low-power clock recovery and data retiming ICs for 2.488Gbps SONET/ SDH applications. The fully integrated phase-locked loop (PLL) recovers a synchronous clock signal from the serial NRZ data input, which is retimed by the recovered clock. An additional 2.488Gbps serial input is available for system loopback diagnostic testing, or this input can be connected to a 155MHz reference clock to maintain a valid clock output in the absence of data transitions. The MAX3877/MAX3878 provide vertical threshold and phase-adjust control to optimize system BER in DWDM applications.
These devices provide both loss-of-lock (active-low LOL) and loss-of-signal (LOS) monitors. Differential CML outputs are provided for both clock and data signals on the MAX3877, and differential PECL outputs are provided for clock and data signals on the MAX3878.
The MAX3877/MAX3878 are designed for both section-regenerator and terminal-receiver applications in OC-48/STM-16 transmission systems. Their jitter performance exceeds all of the SONET/SDH specifications. These devices operate from a single +3.0V to +3.6V supply over a -40°C to +85°C temperature range. Typical power consumption is only 540mW with a +3.3V supply (MAX3878). They are available in a 32-pin TQFP-EP package with an exposed pad, as well as in die form.
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부품번호 suffix: T 또는 T&R = 테잎 앤 릴,
+ = RoHS/lead-free,
# = RoHS/lead 예외.추가 정보: 전체 데이터 시트 또는 부품번호 규칙
*일부 패키지는 크기 편차(variation)를 가지며 이 값은 도면 상에 제시되어 있습니다. “패키지 코드/편차”는 해당 제품이 사용하고 있는 편차를 보여줍니다. 부품번호 suffix에 "+", "#", "-"는 RoHS 준수 상태를 나타냅니다. 패키지 도면에 suffix 문자는 다를 수 있습니다.
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