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DS1WM
동기화 가능한 1-Wire 버스 마스터


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As more 1-Wire® devices become available, more and more users have to deal with the demands of generating 1-Wire signals to communicate to them. This usually requires "bit-banging" a port pin on a microprocessor, and having the microprocessor perform the timing functions required for the 1-Wire protocol. While 1-Wire transmission can be interrupted mid-byte, it cannot be interrupted during the "low" time of a bit time slot; this means that a CPU will be idled for up to 60 microseconds for each bit sent and at least 480 microseconds when generating a 1-Wire reset. The 1-Wire Master helps users handle communication to 1-Wire devices in their system without tying up valuable CPU cycles. Integrated into a user's ASIC as a 1-Wire port, the Verilog or VHDL core uses little chip area (3470 gates plus 2 bond pads).

This circuit is designed to be memory mapped into the user's system and provides complete control of the 1-Wire bus through 8-bit or single commands. The host CPU loads commands, reads and writes data, and sets interrupt control through six individual registers. All of the timing and control of the 1-Wire bus are generated within. The host merely needs to load a command or data and then may go on about its business. When bus activity has generated a response that the CPU needs to receive, the 1-Wire Master sets a status bit and, if enabled, generates an interrupt to the CPU. In addition to write and read simplification, the 1-Wire Master also provides a Search ROM Accelerator function relieving the CPU from having to perform the complex single-bit operations on the 1-Wire bus.

주요기능
  • Memory maps into any standard byte-wide data bus.
  • Eliminates CPU "bit-banging" by internally generating all 1-Wire timing and control signals.
  • Generates interrupts to provide for more efficient programming.
  • Search ROM Accelerator relieves CPU from any single bit operations on the 1-Wire Bus.
  • Capable of running off any system clock from 4MHz to 128MHz.
  • Small size: all digital design, only 3470 gates.
  • Applications include any circuit containing a 1-Wire communication bus.
  • Supports standard and overdrive 1-Wire communication speeds
  • Supports strong pull-up specifications.
  • Master available in both Verilog and VHDL
  • Supports single bit transmissions.
  • Provides added support for long line conditions.

Key Specifications:   1-Wire Interface Products
Part Number Functions Features
DS1WM 
Bus Master Macro
Verilog/VHDL macro for ASIC 1-Wire® bus master
See All 1-Wire Interface Products (4)

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    2007-09-18
    이 페이지는 최근에 변경됨: 2007-09-28




             


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