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MAX104
2.2GHz 트랙/홀드 앰프가 내장된 ±5V, 1Gsps, 8비트 ADC

1Gsps에서 46.2dB의 SINAD를 제공하는 업계 최고 성능의 8비트 ADC


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제품 설명
전체 데이터 시트 (PDF, 896kB)
English Download this datasheet in PDF format다운로드
The MAX104 PECL-compatible, 1Gsps, 8-bit analog-to-digital converter (ADC) allows accurate digitizing of analog signals with bandwidths to 2.2GHz. Fabricated on Maxim's proprietary advanced GST-2 bipolar process, the MAX104 integrates a high-performance track/hold (T/H) amplifier and a quantizer on a single monolithic die.

The innovative design of the internal T/H, which has an exceptionally wide 2.2GHz full-power input bandwidth, results in high performance (greater than 7.5 effective bits) at the Nyquist frequency. A fully differential comparator design and decoding circuitry reduce out-of-sequence code errors (thermometer bubbles or sparkle codes) and provide excellent metastable performance of one error per 1016 clock cycles. Unlike other ADCs that can have errors resulting in false full- or zero-scale outputs, the MAX104 limits the error magnitude to 1LSB.

The analog input is designed for either differential or single-ended use with a ±250mV input voltage range. Dual, differential, PECL-compatible output data paths ensure easy interfacing and include an 8:16 demultiplexer feature that reduces output data rates to one-half the sampling clock rate. The PECL outputs can be operated from any supply between +3V to +5V for compatibility with +3.3V or +5V referenced systems. Control inputs are provided for interleaving additional MAX104 devices to increase the effective system sampling rate.

The MAX104 is packaged in a 25mm x 25mm, 192-contact Enhanced Super-Ball Grid Array (ESBGA™) and is specified over the commercial (0°C to +70°C) temperature range.

주요기능   애플리케이션/용도
  • 1Gsps Conversion Rate
  • 2.2GHz Full-Power Analog Input Bandwidth
  • >7.5 Effective Bits at fIN = 500MHz (Nyquist Frequency)
  • ±0.25LSB INL and DNL
  • 50Ω Differential Analog Inputs
  • ±250mV Input Signal Range
  • On-Chip, +2.5V Precision Bandgap Voltage Reference
  • Latched, Differential PECL Digital Outputs
  • Low Error Rate: 10-16 Metastable States at 1Gsps
  • Selectable 8:16 Demultiplexer
  • Internal Demux Reset Input with Reset Output
  • 192-Contact ESBGA Package

 
  • 자동 시험 장비 (ATE)
  • 디지털 오실로스코프
  • 디지털 RF/IF 신호 처리
  • 직접 RF 다운컨버전
  • 고에너지 물리학
  • 고속 데이터 수집
  • 레이더/소나(Sonar)/ECM 시스템

    Key Specifications:   High-Speed ADCs (> 5Msps)
    Part Number Input Channels Resolution (Bits) Sample Rate (max) (Msps) AC Specs @ fIN (MHz) SFDR (dBc) ENOB (bits) SINAD (dB) SNR (dB) THD (db) INL (±LSB) DNL (±LSB) Full-Power BW (MHz) Typ. Supply Current (mA) Data Bus Interface Smallest Available Package (max w/pins) (mm2)
    MAX104  1 8 1000 500 52.3 7.55 46.2 47 -52.5 0.25 0.25 2200 1078 µP/8
    Demuxed
    LVPECL
    630
    See All High-Speed ADCs (> 5Msps) (77)

    다이어그램
    MAX104: Typical Operating Circuit
    일반 동작 회로

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  • 익일에 제공되는 애플리케이션 엔지니어의 제품 선택 조언
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    문서 레퍼런스 19-1459; 개정판 2; 2002-06-20
    이 페이지는 최근에 변경됨: 2009-04-13


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