Abstract: Although positive-referenced emitter-coupled logic (PECL) remains on of the standard logic families used for high-speed inputs and outputs in framer devices, the high current consumption of these outputs calls for an intermediate solution. Therefore, Maxim has released the MAX3881 and MAX3891 deserializer and serializer mux/demux chips, using single-ended PECL drivers and single-ended PECL receivers I/O for the parallel I/O. When switching between single-ended and differential architectures, the unused inputs/outputs must be connected properly. The application note you have requested is available in Acrobat PDF format: APPLICATION NOTE 488: HFAN-01.0.1: Interfacing Single-Ended PECL to Differential PECL and Differential PECL to Single-Ended PECL (PDF, 44kB) A free Acrobat PDF reader is available from: http://www.adobe.com/products/acrobat/readstep.html We Want Your Feedback! Automatic Updates Would you like to be automatically notified when new application notes are published in your areas of interest? Sign up for EE-Mail™. More Information   APP 488: Jan 04, 2001 MAX3881 +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery Full Data Sheet (PDF, 240kB) MAX3891 16:1 Serializer, 3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs Full Data Sheet (PDF, 528kB)   Download, PDF Format (44kB)  AN488, AN 488, APP488, Appnote488, Appnote 488