Abstract: The DS80C400 datasheet mentions that the DS80C400 RSTOL output should not be connected to the network PHY's reset input. This application note describes the reason for this restriction and shows how the PHY reset input should be used.
Overview
The DS80C400 data sheet mentions that the DS80C400 RSTOL output should not be connected to the network PHY's reset input. This application note describes the reason for this restriction, and shows how the PHY reset input should be used.
Requirements
This application note assumes the use of a DS80C400 rev. B1 networked microcontroller and an Intel LXT972A Ethernet PHY. Similar considerations apply to other manufacturers' PHYs, but pinout and pin names may differ.
This application note does not apply to the DS80C410 or DS80C411.
Background
The DS80C400 rev. B1 will not receive network packets when there is no clock signal on the receive clock pin (RXCLK) during reset (other than power-up). When the DS80C400 reset output (RSTOL) and the PHY reset input (RESET) are connected, the DS80C400 puts the PHY into reset—and the PHY is unable to generate the receive clock signal.
Solution
The solution is to not connect the DS80C400 RSTOL and the PHY's reset input RESET as documented in the DS80C400 data sheet.
Configuration Pin Sampling
Additional testing has shown that some LXT972A PHYs do not always sample the state of the configuration pins correctly (LED/CFG1, LED/CFG2 and LED/CFG3). This can result in 10Mb operation even though 100Mb were requested, or nonfunctioning LEDs. A 1uF capacitor between the PHY's reset input (RESET) and ground solves this problem.
Suggested Circuit
The highlighted part of the schematic (Figure 1) shows the proper PHY reset connection.
Figure 1. DS80C400 and PHY reset.
TINIS400 Socket
The TINIs400 socket has been modified to sever the connection between RESET and RSTOL. Figure 2 shows the modification. (TINIs400 ships with this modification applied at the factory.)
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