Abstract: This application note describes how the DS2141A, DS2143, DS2151, and DS2153 interface to the Siemens PEB2045. This note also shows waveforms and timing diagrams of different pins that are used for interfacing to the PEB2045. Notes: The PEB2045 is operated in the 4 MHz standard configuration mode. Gates #1 and #2 are used to condition the frame sync to meet the timing requirements of the PEB2045. Both the transmit and receive elastic stores in the DS2141A, DS2151 are enabled; the DS2143, DS2153 only need the receive side elastic store enabled. The DS2141A, DS2151 is set up to output a frame sync at the RSYNC and TSYNC pins while the DS2143, DS2153 is set up to output a frame sync at RSYNC and input a frame sync at TSYNC. The DS2141A, DS2143, DS2151 and DS2153 is set up for SYSCLK operation of 2.048 MHz. The elastic stores provide controlled slip operation. In "looped-timed" applications, close switch 1 and open switch 2. In applications that cannot handle controlled slips, close switches 1 and 4 and open switches 2 and 3. In DS2151 and DS2153 applications, the line interface block is included onboard the device. Timing between the devices is shown below: 관련 부품   APP 315: May 08, 2001 DS2141A T1 컨트롤러 전체 데이터 시트 (PDF, 480kB) 무료 샘플 DS2143 E1 컨트롤러 전체 데이터 시트 (PDF, 568kB) 무료 샘플 자동 업데이트 관심 분야의 애플리케이션 노트가 나올 때 자동으로 업데이트를 원하십니까? 그렇다면 EE-Mail™을 신청하십시오. We Want Your Feedback! 의견을 보내주세요! 위 내용이 도움이 되셨나요? 여러분의 의견을 기다립니다 — Maxim은 보내주신 정정이나 제안사항을 반영하고 있습니다. 이 페이지를 평가하고 의견을 보내주십시오.   다운로드, PDF 형식 (28kB)  AN315, AN 315, APP315, Appnote315, Appnote 315